? semiconductor components industries, llc, 2002 august, 2002 rev. 8 1 publication order number: mc10h680/d mc10h680, mc100h680 4-bit differential ecl bus to ttl bus transceiver the mc10h/100h680 is a dual supply 4bit differential ecl bus to ttl bus transceiver. it is designed to allow the system designer to no longer be limited in bus speed associated with standard ttl busses. using a differential ecl bus will increase the frequency of operation and increase noise immunity. both the ttl and the ecl ports are capable of driving a bus. the ecl outputs have the ability to drive 25 , allowing both ends of the bus line to be terminated in the characteristic impedance of 50 . the ttl outputs are specified to source 15 ma and sink 48 ma, allowing the ability to drive highly capacitive loads. the ecl output levels are v oh approximately equal to 1.0 v and v ol cutoff equal to 2.0 v (vtt). when the ecl ports are disabled both eiox and eioxb go to the v ol cutoff level. the ecl input receivers have special circuitry which detects this disabled condition, prevents oscillation, and forces the ttl output to the low state. the noise margin in this disabled state is greater than 600 mv. multiple ecl v cco pins are utilized to minimize switching noise. the ttl ports have standard levels. the ttl input receivers have pnp input devices to significantly reduce loading. multiple ttl power and ground pins are utilized to minimize switching noise. the control pins (edir and eceb) of the 10h version is compatible with mecl 10h ecl logic levels. the control pins of the 100h version are compatible with 100k levels. ? differential ecl bus (25 ) i/o ports ? high drive ttl bus i/o ports ? extra ttl and ecl power/ground pins to minimize switching noise ? dual supply ? direction and chip enable control pins figure 1. pinout: 28lead plcc (top view) tio2 gt3 vt2 gt4 tio3 tceb eceb eio0 eio0b ei01 eio1b v cco1 v ee v cco2 1 56 7891011 25 24 23 22 21 20 19 26 27 28 2 3 412 13 14 15 16 17 18 t101 gt2 vt1 gt1 tio0 tdir edir eio3b v cco4 eio3 v cce eio2b v cco3 eio2 device package shipping ordering information mc10h680fn plcc28 37 units/rail marking diagram a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 10h680 awlyyww 1 mc100h680fn plcc28 37 units/rail http://onsemi.com
mc10h680, mc100h680 http://onsemi.com 2 pin descriptions pin symbol function 1 gt1 ttl ground 1 2 tio0 ttl i/o bit 0 3 tdir ttl direction control 4 edir ecl direction control 5 eio0 ecl i/o bit 0 6 vcco1 ecl vcc 1 (0v) outputs 7 eio0b ecl i/o bit 0 bar 8 vee ecl supply (5.2/4.5v) 9 eio1 ecl i/o bit 1 10 vcco2 ecl vcc 2 (0v) outputs 11 eio1b ecl i/o bit 1 bar 12 eio2 ecl i/o bit 2 13 vcco3 ecl vcc 3 (0v) outputs 14 eio2b ecl i/o bit 2 bar 15 vcce ecl vcc (0v) 16 eio3 ecl i/o bit 3 17 vcco4 ecl vcc 4 (0v) outputs 18 eio3b ecl i/o bit 3 bar 19 eceb ecl chip enable bar control 20 tceb ttl chip enable bar control 21 tio3 ttl i/o bit 3 22 gt4 ttl ground 4 23 vt2 ttl supply 2 (5v) 24 gt3 ttl ground 3 25 tio2 ttl i/o bit 2 26 tio1 ttl i/o bit 1 27 gt2 ttl ground 2 28 vt1 ttl supply 1 (5v) truth table tdir e direction control ttl levels edir e direction control ecl levels tceb e chip enable bar control ttl levels eceb e chip enable bar control ecl levels tin e ttl input tout e ttl output ein e ecl input einb e ecl input bar eout e ecl output eoutb e ecl output bar h e high l e low lc e ecl low cutoff (vtt = 2.0 v) x e don't care z e high impedance eceb tceb edir tdir ein einb eout eoutb tin tout comments h x x x x x lc lc x z ecl and ttl outputs disabled x h x x x x lc lc x z ecl and ttl outputs disabled l l h x h lc na h ecl to ttl direction l l h x lc h na l ecl to ttl direction l l h x lc lc na l ecl to ttl direction (ll cond.) l l x h h lc na h ecl to ttl direction l l x h lc h na l ecl to ttl direction l l x h lc lc na l ecl to ttl direction (ll cond.) l l l l na na h lc h ttl to ecl direction l l l l na na lc h l ttl to ecl direction
mc10h680, mc100h680 http://onsemi.com 3 absolute ratings (do not exceed): power supply voltage v ee (ecl) 8.0 to 0 vdc power supply voltage v cct (ttl) 0.5 to +7.0 vdc input voltage v i (ecl) v i (ttl) 0.0 to v ee 0.5 to +7.0 vdc disabled 3state output v out (ttl) 0.0 to v cct vdc output source current continuous i out (ecl) 100 madc output source current surge i out (ecl) 200 madc storage temperature t stg 65 to 150 c operating temperature t amb 0.0 to +75 c ecl dc characteristics: v cct = +5.0 v 10%, v ee = 5.2 5% (10h version) ; v ee = 4.2 v to 5.5 v (100h version) test t a = 0 c t a = 25 c t a = 75 c t es t symbol parameter min max min max min max unit condition i ee supply current/ecl 110 110 110 ma i inh input high current 225 145 145 a i inl input low current 0.5 0.5 0.3 a v oh v ol output high voltage output low voltage 1100 2.1 840 2.03 1100 2.1 810 2.03 1100 2.1 735 2.03 mv v 25 to 2.1 v control inputs only 10h ecl dc characteristics: v cct = +5.0 10%, v ee = 5.2 5% test t a = 0 c t a = 25 c t a = 75 c t es t symbol parameter min max min max min max unit condition v ih v il input high voltage input low voltage 1170 1950 840 1480 1130 1950 810 1480 1070 1950 735 1450 mv control inputs only 100h ecl dc characteristics: v cct = +5.0 10%, v ee = 4.2 v to 5.5 v test t a = 0 c t a = 25 c t a = 75 c t es t symbol parameter min max min max min max unit condition v ih v il input high voltage input low voltage 1165 1810 880 1475 1165 1810 880 1475 1165 1810 880 1475 mv
mc10h680, mc100h680 http://onsemi.com 4 ttl dc characteristics: v cct = +5.0 v 10%, v ee = 5.2 5% (10h version) ; v ee = 4.2 v to 5.5 v (100h version) test t a = 0 c t a = 25 c t a = 75 c t es t symbol parameter min max min max min max unit condition v ih v il standard input standard input 2.0 0.8 2.0 0.8 2.0 0.8 vdc v ik input clamp 1.2 1.2 1.2 vdc i in = 18 ma v oh output high voltage output high voltage 2.5 2.0 2.5 2.0 2.5 2.0 v i oh = 3.0 ma i oh = 15 ma v ol output low voltage 0.55 0.55 0.55 v i ol = 48 ma i ih * ttl (input high) ttl (input high) 20 100 20 100 20 100 a v in = 2.7 v v in = 7.0 v i il * ttl (input low) 0.6 0.6 0.6 ma v in = 0.5 v i ccl supply current 75 75 75 ma i cch supply current 70 70 70 ma i ccz supply current 70 70 70 ma i os output short circuit current 100 225 100 225 100 225 ma v out = 0 v * note: ttl control inputs only ttl i/o dc characteristics only test t a = 0 c t a = 25 c t a = 75 c t es t symbol parameter min max min max min max unit condition i ih/iozh i il/iozl output disable current 70 200 70 200 70 200 a v out = 2.7 v v out = 0.5 v ecl to ttl direction / ac test test t a = 0 c t a = 25 c t a = 75 c t es t symbol parameter waveforms min max min max min max unit condition t plh t phl propagation delay to output 2, 4 2.7 4.8 2.7 4.8 2.7 4.8 ns c l = 50 pf t pzh t pzl eceb to output enable time 2, 5, 6 3.5 3.5 6.5 6.0 3.5 3.5 6.5 6.0 3.7 3.7 6.7 6.4 ns c l = 50 pf t phz t plz eceb to output disable time 2, 5, 6 3.5 3.5 8.6 6.5 3.5 3.5 8.6 6.5 3.7 3.7 8.8 7.3 ns c l = 50 pf t pzh t pzl tceb to output enable time 2, 5, 6 5.7 5.4 7.7 6.9 5.7 5.4 7.7 6.9 5.9 5.9 7.9 7.4 ns c l = 50 pf t phz t plz tceb to output disable time 2, 5, 6 4.0 4.0 8.5 5.8 4.1 4.2 8.4 6.0 4.2 4.7 8.3 6.5 ns c l = 50 pf t r /t f 1.0 to 2.0 vdc 3 0.4 1.5 0.4 1.5 0.4 1.5 ns c l = 50 pf ttl to ecl direction / ac test test t a = 0 c t a = 25 c t a = 75 c t es t symbol parameter waveforms min max min max min max unit condition t plh t phl propagation delay to output 1, 4 1.8 4.6 1.8 4.6 2.0 4.9 ns 25 to 2.0 v t plh t phl eceb to output 1, 4 2.9 5.1 3.0 5.2 3.4 5.7 ns 25 to 2.0 v t plh t phl tceb to output 1, 4 3.4 6.3 3.5 6.6 3.8 7.4 ns 25 to 2.0 v t r /t f output rise/fall time 20%80% 1, 3 1.0 3.4 1.0 3.4 1.0 3.4 ns 25 to 2.0 v
mc10h680, mc100h680 http://onsemi.com 5 figure 2. block diagram toe eoe control inputs ecl i/o ttl i/o v ee v cce v cct2 v cct1 v cco1 gnd1 v cco2 gnd2 v cco3 gnd3 gnd4 v cco4 tio3 eio3 eio3 tio2 eio2 eio2 tio1 eio1 eio1 ece tce edir tdir tio0 eio0 eio0 50 coax v ee v cc & v cco in out oscilloscope ch a ch b use 0.1 f capacitors for decoupling. device under test pulse generator figure 3. switching circuit ecl ecl device under test 50 pf r2 500 r1 500 all others +7 v open t pzl , t plz ttl 50 use oscilloscope internal 50 load for termination. 50 coax 50 coax figure 4. switching circuit
mc10h680, mc100h680 http://onsemi.com 6 50%/1.5 v v in t pd++ t pd-- 50%/1.5 v v out v out t rise t fall 80%/2.0 v 20%/1.0 v ecl/ttl ecl/ttl ttl ttl ve ve 1.5 v 1.5 v 1.5 v t plz t pzl v out v ol 0.3 v ve ve 1.5 v 1.5 v 1.5 v t phz t pzh v out v oh ?? ? ? ? ? ?? ? ?? figure 5. waveforms: rise and fall times figure 6. propagation delay e single ended figure 7. 3state output low enable and disable times figure 8. 3state output high enable and disable times v tt figure 9. ecl i/o link application recommended termination (directional control intentionally excluded) 50 50 v tt 50 50 ttl i/o ecl i/o ttl i/o ecl i/o 1 of 4 1 of 4 waveforms
mc10h680, mc100h680 http://onsemi.com 7 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e n m l v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t t b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view dd s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 --- 1.02 ---
mc10h680, mc100h680 http://onsemi.com 8 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 291 kamimeguro, meguroku, tokyo, japan 1530051 phone : 81357733850 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10h680/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada
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